The present invention relates to synthesis of a design block of an integrated circuit, and more specifically, to critical region identification.
The development of an integrated circuit (IC) involves a number of steps, some of which are performed iteratively. Generally, a logic phase, which involves the design of the digital logic circuits of the IC, is followed by a physical design phase, in which the IC is subdivided into logic blocks for purposes of design and synthesis. As the size and complexity of these blocks increases, convergence of the design in terms of meeting all timing and power efficiency goals can take longer. This is because an improvement in timing or power consumption in one area or region of a block may adversely affect those same parameters in a different region.